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HI-3182, HI-3183, HI-3184, HI-3185 HI-3186, HI-3187, HI-3188
August 2006
ARINC 429 DIFFERENTIAL LINE DRIVER
PIN CONFIGURATION
VREF 1 GND (See Note * ) 2 SYNC 3 DATA (A) 4 CA 5 AOUT 6 -V 7 14 V1 13 CLOCK 12 DATA (B) 11 CB 10 BOUT 9 +V 8 GND
GENERAL DESCRIPTION
The HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187 and HI-3188 bus interface products are silicon gate CMOS devices designed as a line driver in accordance with the ARINC 429 bus specifications. In addition to being functional upgrades of Holt's HI-8382 & HI-8383 products, they are also alternate sources for the HS-3182 ( Intersil/Harris), the RM3182 (Fairchild /Raytheon) and a variety of similar line driver products from other manufacturers. Inputs are provided for clocking and synchronization. These signals are AND'd with the DATA inputs to enhance system performance and allow the HI-318X series of products to be used in a variety of applications. Both logic and synchronization inputs feature built-in 2,000V minimum ESD input protection as well as TTL and CMOS compatibility. The differential outputs of the HI-318X series of products are programmable to either the high speed or low speed ARINC 429 output rise and fall time specifications through the use of two external capacitors. The output voltage swing is also adjustable by the application of an external voltage to the VREF input. Products with 0, 13 or 37.5 ohm resistors in series with each ARINC output are available. In addition, the HI-3182, HI-3184 and HI-3187 products also have a fuse in series with each output. The HI-318X series of line drivers are intended for use where logic signals must be converted to ARINC 429 levels such as when using an ASIC, the HI-3282/HI-8282A ARINC 429 Serial Transmitter/Dual Receiver, the HI-6010 ARINC 429 Transmitter/Receiver or the HI-8783 ARINC Interface Device. Holt products are readily available for both industrial and military applications. Please contact the Holt Sales Department for additional information.
(Top View)
HI-3184PS, HI-3185PS, HI-3186PS & HI-3187PS
14 - PIN PLASTIC SMALL OUTLINE (ESOIC)** NB
Notes: * Pin 2 may be left floating ** Thermally Enhanced SOIC Package
(See Page 6 for additional package pin configurations)
FUNCTION + _
ARINC 429 DIFFERENTIAL LINE DRIVER
FEATURES
! Low power CMOS ! TTL and CMOS compatible inputs ! Programmable output voltage swing ! Adjustable ARINC rise and fall times ! Plastic 14 & 16-pin thermally enhanced SOIC packages available ! Pin-for-Pin alternative for Intersil/Fairchild applications ! Operates at data rates up to 100 Kbits ! Overvoltage protection ! Industrial and Military temperature ranges
TRUTH TABLE
SYNC CLOCK DATA(A) DATA(B) AOUT X L H H H H L X H H H H X X L L H H X X L H L H 0V 0V 0V -VREF +VREF 0V BOUT COMMENTS 0V 0V 0V +VREF -VREF 0V NULL NULL NULL LOW HIGH NULL
(DS3182 Rev. H )
HOLT INTEGRATED CIRCUITS www.holtic.com
08/06
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
FUNCTIONAL DESCRIPTION
The SYNC and CLOCK inputs establish data synchronization utilizing two AND gates, one for each data input (figure 2). Each logic input, including the power enable (STROBE) input, are TTL/CMOS compatible. Figure 1 illustrates a typical ARINC 429 bus application. Three power supplies are necessary to operate the HI-3182; typically +15V, -15V and +5V. The chip also works with 12V supplies. The +5V supply can also provide a reference voltage that determines the output voltage swing. The differential output voltage swing will equal 2VREF. If a value of VREF other than +5V is needed, a separate +5V power supply is required for pin V1. With the DATA (A) input at a logic high and DATA (B) input at a logic low, AOUT will switch to the +VREF rail and BOUT will switch to the -VREF rail (ARINC HIGH state). With both data input signals at a logic low state, the outputs will both switch to 0V (ARINC NULL state). The driver output impedance, ROUT, is nominally 75, 26 or 0 ohms depending on the option chosen. The rise and fall times of the outputs can be calibrated through the selection of two external capacitor values that are connected to the CA and CB input pins. Typical values for high-speed operation (100KBPS) are CA = CB = 75pF and for low-speed operation (12.5 to 14KBPS) CA = CB = 500pF. The CA and CB pins swing between +5V and ground allowing the switching of capacitor values with an external singlesupply analog switch. The ARINC outputs can be put in a tri-state mode by applying a logic high to the STROBE input pin. If this feature is not being used, the pin should be tied to ground. The STROBE
function is not available in the 14 & 16-pin SOIC package configurations where the pin is internally connected to ground. The ARINC outputs of the HI-3182, HI-3184 and HI-3187 are protected by internal fuses capable of sinking between 800 900 mA for short periods of time (125ms). The Vref pin has an internal pull-up resistor to V+, allowing the use of a simple external zener diode to set the reference voltage.
POWER SUPPLY SEQUENCING
The power supplies should be controlled to prevent large currents during supply turn-on and turn-off. The recommended sequence is +V followed by V1, always ensuring that +V is the most positive supply. The -V supply is not critical and can be asserted at any time.
+5V +15V
VREF
DATA (A)
V1 SYNC CLOCK
AOUT
+V
INPUTS
DATA (B)
CA CB STROBE GND -V
TO ARINC BUS
BOUT
-15V
Figure 1. ARINC 429 BUS APPLICATION
VREF
+V
CA
Shorted on HI-3186, HI-3187, HI-3188
A OUT
DATA (A) LEVEL SHIFTER AND SLOPE CONTROL (A) CLOCK 24.5W OUTPUT DRIVER (A) CL SYNC LEVEL SHIFTER AND SLOPE CONTROL (B) 24.5W OUTPUT DRIVER (B) 13W RL 13W FA
FB
DATA (B)
V1
STROBE
CURRENT REGULATOR
Shorted on HI-3183, HI-3186 HI-3187, HI-3188
Shorted on HI-3183, HI-3185 HI-3186, HI-3188
GND
-V
CB
B OUT
Figure 2. FUNCTIONAL BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS 2
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
PIN DESCRIPTIONS
SYMBOL
VREF STROBE SYNC DATA (A) CA AOUT -V GND +V BOUT CB DATA (B) CLOCK V1
FUNCTION
ANALOG INPUT INPUT INPUT INPUT OUTPUT POWER POWER POWER OUTPUT INPUT INPUT INPUT POWER
DESCRIPTION
Ref. voltage used to determine output voltage swing. Pin sources current to allow use of a zener reference. A logic high tri-states the ARINC outputs. Not available in the 14-pin SOIC package (tied to GND internally). Synchronizes data inputs Data input terminal A Connection for DATA (A) slew-rate capacitor ARINC output terminal A -12V to -15V 0.0V +12V to +15V ARINC output terminal B Connection for DATA (B) slew-rate capacitor Data input terminal B Synchronizes data inputs +5V 5%
ABSOLUTE MAXIMUM RATINGS
All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified)
PARAMETER
Differential Voltage Supply Voltage
SYMBOL
VDIF +V -V V1 VREF VIN
CONDITIONS
Voltage between +V and -V terminals
OPERATING RANGE
MAXIMUM
40
UNIT
V V V V V V V V
+10.8 to +16.5 -10.8 to -16.5 +5 5% For ARINC 429 For Applications other than ARINC +5 5% 1.5 to 6
+7 6 6 > GND -0.3 < V1 +0.3
Voltage Reference Input Voltage Range Output Short-Circuit Duration Output Overvoltage Protection Operating Temperature Range Storage Temperature Range Lead Temperature Junction Temperature
See Note: 1 See Note: 2 TA TSTG High-temp & Military Industrial Ceramic & Plastic Soldering, 10 seconds TJ -55 to +125 -40 to +85 -65 to +150 +275 +175 C C C C C
Note 1. Heatsinking may be required for continuous Output Short Circuit at +125C and for 100KBPS at +125C. Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater than 12.0V with respect to GND. (HI-3182, 3184 & 3187 only) NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HOLT INTEGRATED CIRCUITS 3
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
DC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Supply Current +V (Operating) Supply Current -V (Operating) Supply Current V1 (Operating) Reference Pin Current VREF (Operating) Supply Current +V (During Short Circuit Test) Supply Current -V (During Short Circuit Test) Output Short Circuit Current (Output High) Output Short Circuit Current (Output Low) Input Current (Input High) Input Current (Input Low) Input Voltage High Input Voltage Low Output Voltage High (Output to Ground) Output Voltage Low (Output to Ground) Output Voltage Null Input Capacitance
SYMBOL ICCOP (+V) ICCOP (-V) ICCOP (V1) ICCOP (VREF) ISC (+V) ISC (-V) IOHSC IOLSC IIH IIL VIH VIL VOH VOL VNULL CIN
No Load No Load No Load
CONDITION
(0 - 100KBPS) (0 - 100KBPS) (0 - 100KBPS)
MIN
-16
TYP
MAX UNITS
+16 500 mA mA A mA mA mA -80 mA mA 1.0 A A V 0.5 V V V mV pF +VREF +.25 -VREF +.25 +250
No Load, VREF = 5V (0 - 100KBPS) Short to Ground Short to Ground Short to Ground Short to Ground (See Note: 1) (See Note: 1)
-1.0 -150 +80 -1.0 2.0
-0.4
-0.15 150
VMIN=0 (See Note: 2) VMIN=0 (See Note: 2)
No Load No Load No Load
See Note 1
(0 -100KBPS) (0 -100KBPS) (0-100KBPS)
+VREF -.25 -VREF -.25 -250 15
Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter. Note 2. Interchangeability of force and sense is acceptable.
AC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Rise Time ( A OUT , B OUT ) Fall Time ( A OUT , B OUT ) Propagtion Delay Input to Output Propagtion Delay Input to Output
SYMBOL tR tF t PLH t PHL
CONDITION C A = C B = 75pF C A = C B = 75pF C A = C B = 75pF C A = C B = 75pF
See Figure 3. See Figure 3. See Figure 3. See Figure 3.
MIN
1.0 1.0
TYP
MAX UNITS
2.0 2.0 3.0 3.0 s s s s
DATA (A) 0V DATA (B) 0V VREF
50% 50% ADJUST BY CA
2.0V 0.5V 2.0V 0.5V
+4.75V to +5.25V
AOUT 0V
ADJUST BY CA
-VREF
50% 50%
-4.75V to -5.25V
ADJUST BY CB ADJUST BY CB
tPHL
+VREF
+4.75V to +5.25V -4.75V to -5.25V
HIGH NULL
BOUT 0V
-VREF
tPLH
tR
DIFFERENTIAL OUTPUT 0V
2VREF
+9.5V to +10.5V
(AOUT - BOUT)
NOTE: OUTPUTS UNLOADED
tF
-2VREF
LOW
-9.5V to -10.5V
Figure 3. SWITCHING WAVEFORMS
HOLT INTEGRATED CIRCUITS 4
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
HI-318X PACKAGE THERMAL CHARACTERISTICS
MAXIMUM ARINC LOAD
PACKAGE STYLE
1
3, 6, 7
HEAT SINK Unsoldered Soldered Unsoldered Soldered N/A
OJA (C/W) 82 65 51 28 70
SUPPLY CURRENT 20 mA 20 mA 20 mA 20 mA 25 mA
2
JUNCTION TEMPERATURE, Tj TA = 25C TA = 85C TA = 125C 57C 51C 45C 36C 56C 117C 111C 105C 96C 110C 157C 151C 145C 136C 150C
14-pin Thermally Enhanced Plastic SOIC (ESOIC) 14-pin Thermally Enhanced Plastic SOIC (ESOIC) 28-pin Plastic PLCC
AOUT and BOUT Shorted to Ground
PACKAGE STYLE
1
3, 4, 5, 6, 7
HEAT SINK Unsoldered Soldered Unsoldered Soldered N/A
OJA (C/W) 82 65 51 28 70
SUPPLY CURRENT 36 mA 36 mA 40 mA 40 mA 63 mA
2
JUNCTION TEMPERATURE, Tj TA = 25C TA = 85C TA = 125C 57C 78C 64C 53C 100C 147C 138C 124C 113C 150C 187C 178C 164C 153C 182C
14-pin Thermally Enhanced Plastic SOIC (ESOIC) 14-pin Thermally Enhanced Plastic SOIC (ESOIC) 28-pin Plastic PLCC
Notes: 1. All data taken in still air on devices soldered to a single layer copper PCB (3" X 4.5" X .062"). 2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8. 3. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF as this is considered unrealistic for high speed operation. 4. Similar results would be obtained with AOUT shorted to BOUT. 5. For applications requiring survival with continuous short circuit, operation above Tj = 175C is not recommended. 6. Data will vary depending on air flow and the method of heat sinking employed. 7. Current values listed are for each of the +V and -V supplies.
HEAT SINK - ESOIC PACKAGES
Both the 14-pin and 16-pin thermally enhanced SOIC packages are used for HI-318X products. These ESOIC packages include a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the chip and can be soldered to any ground or power plane. However, since the chip's substrate is at +V, connecting the heat sink to this power plane is recommended to avoid coupling noise into the circuit.
HOLT INTEGRATED CIRCUITS 5
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
ADDITIONAL PIN CONFIGURATIONS (See page 1 for 14-Pin Small Outline SOIC)
HI-3182PS, HI-3183PS, HI-3188PS
VREF - 1 GND (See Note * ) - 2 SYNC - 3 DATA(A) - 4 CA - 5 AOUT - 6 -V - 7 GND - 8 16 - V1 15 - N/C 14 - CLOCK 13 - DATA(B) 12 - CB 11 - BOUT 10 - N/C 9 - +V N/C DATA (A) N/C N/C CA N/C N/C
5 6 7 8 9 10 11 12 13 14 15 16 17 18
SYNC STROBE N/C VREF V1 N/C N/C
4 3 2 1 28 27 26 25 24
HI-3182PJ 23 22 HI-3183PJ 21
20 19
CLOCK N/C DATA (B) CB N/C N/C N/C
Notes: * Pin 2 may be left floating ** Thermally Enhanced SOIC package
16 - PIN PLASTIC SMALL OUTLINE (ESOIC)**
28 - PIN PLASTIC PLCC
29 28 27 26 25 24 23 22 21
CLOCK V1 N/C VREF STROBE SYNC N/C
30 31 32 1 2 3 4 56 7 8 9 10 11 12 13
20 19
HI-3182CJ HI-3183CJ
18 17 16 15 14
N/C N/C +V GND N/C -V N/C
N/C DATA (A) N/C N/C CA N/C N/C
SYNC STROBE N/C VREF V1 N/C N/C
4 5 6 7 8 9 10 11 3 2 1 28 27 26 25 24
N/C N/C N/C N/C DATA(B) CB N/C N/C BOUT
N/C AOUT -V GND +V BOUT N/C
HI-3182CL HI-3183CL
23 22 21 20
19 12 13 14 15 16 17 18
CLOCK N/C DATA (B) CB N/C N/C N/C
N/C N/C N/C DATA(A) CA N/C N/C N/C AOUT
32 - PIN CERQUAD
28 - PIN CERAMIC LCC
VREF 1
16 V1 15 N/C 14 CLOCK 13 DATA(B) 12 CB 11 BOUT 10 N/C 9 +V
N/C AOUT -V GND +V BOUT N/C
VREF 1
16 V1 15 N/C 14 CLOCK 13 DATA(B) 12 CB 11 BOUT 10 N/C 9 +V
HI-3182CD HI-3183CD
16 - PIN CERAMIC SIDE BRAZED DIP
STROBE 2 SYNC 3 DATA(A) 4 CA 5 AOUT 6 -V 7 GND 8
HI-3182CR HI-3183CR
16 - PIN CERDIP
STROBE 2 SYNC 3 DATA(A) 4 CA 5 AOUT 6 -V 7 GND 8
HOLT INTEGRATED CIRCUITS 6
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
ORDERING INFORMATION
HI - 318x x x - xx (Ceramic)
PART NUMBER I T M PART NUMBER CD CJ CL CR PART NUMBER 3182 3183 TEMPERATURE RANGE -40C TO +85C -55C TO +125C -55C TO +125C PACKAGE DESCRIPTION 16 PIN CERAMIC SIDE BRAZED DIP 32 PIN J-LEAD CERQUAD (not available with `M' flow) 28 PIN CERAMIC LEADLESS CHIP CARRIER (LCC) 16 PIN CERDIP (not available with `M' flow) OUTPUT SERIES RESISTANCE FUSE 37.5 Ohms 13 Ohms YES NO FLOW I T M BURN IN NO NO YES LEAD FINISH (1) Gold (`M' flow: solder) Solder Gold (`M' flow: solder) Solder
HI - 318xxx x x (Plastic)
PART NUMBER Blank F PART NUMBER I T M (2) PART NUMBER 3182PJ 3182PS 3183PJ 3183PS 3184PS 3185PS 3186PS 3187PS 3188PS LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE -40C TO +85C -55C TO +125C -55C TO +125C PACKAGE DESCRIPTION 28 PIN PLASTIC J-LEAD PLCC 16 PIN PLASTIC SMALL OUTLINE - WB (ESOIC) 28 PIN PLASTIC J-LEAD PLCC 16 PIN PLASTIC SMALL OUTLINE - WB (ESOIC) 14 PIN PLASTIC SMALL OUTLINE - NB (ESOIC) 14 PIN PLASTIC SMALL OUTLINE - NB (ESOIC) 14 PIN PLASTIC SMALL OUTLINE - NB (ESOIC) 14 PIN PLASTIC SMALL OUTLINE - NB (ESOIC) 16 PIN PLASTIC SMALL OUTLINE - WB (ESOIC) FLOW I T M BURN IN NO NO YES OUTPUT SERIES RESISTANCE FUSE 37.5 Ohms 37.5 Ohms 13 Ohms 13 Ohms 37.5 Ohms 37.5 Ohms 13 Ohms 13 Ohms 13 Ohms YES YES NO NO YES NO NO YES NO
Legend:
ESOIC - Thermally Enhanced Small Outline Package (SOIC w/built-in heat sink) NB - Narrow Body WB - Wide Body (1) Gold terminal finish is Pb-Free, RoHS compliant. (2) Only available with `3182PJ'.
HOLT INTEGRATED CIRCUITS 7
HI-318X PACKAGE DIMENSIONS
inches (millimeters)
14-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB (Narrow Body, Thermally Enhanced)
.3406 .0039 (8.651 .099) .00865 .00115 (.220 .029)
Package Type: 14H 14HNE
.280 TYP. (7.112) TYP.
.236 .008 (6.00 .20)
Top View
.1535 .0035 (3.899 .089)
.110 TYP. (2.794) TYP.
Bottom View
.0165 .0035 (.419 ..089)
Detail A
.061 .007 (1.549 .178)
Electrically isolated metal heat sink on bottom of package (Connect to any ground or power plane for optimum thermal dissipation)
0 to 8
.050 .010 (1.270 .254) .033 .017 (.838 .432)
Detail A
.0069 .0029 (.175 .074)
16-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB (Narrow Body, Thermally Enhanced)
.3898 .0039 (9.901 .099) .00865 .00115 (.220 .029)
Package Type: 16HNE
.280 TYP. (7.112) TYP.
.236 .008 .008 (6.00 .20) .20)
Top View
.1535 .0035 (3.899 .089)
.110 TYP. (2.794) TYP.
Bottom View
.0165 .0035 (.419 ..089)
Detail A
.061 .007 (1.549 .178)
Electrically isolated metal heat sink on bottom of package (Connect to any ground or power plane for optimum thermal dissipation)
0 to 8
.050 .010 .010 (1.270 .254) .254) .033 .017 (.838 .432)
Detail A
.0069 .0029 (.175 .074)
HOLT INTEGRATED CIRCUITS 8
HI-318X PACKAGE DIMENSIONS
inches (millimeters)
16-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced)
.405 .008 (10.287 .203) .0105 .0015 (.2667 .0381)
Package Type: 16HWE
.240 .010 (6.096 .254)
.4065 .0125 (10.325 .318)
Top View
.295 .004 (7.493 .102)
.190 .010 (4.826 .254)
Bottom View
Detail A
Electrically isolated metal heat sink on bottom of package
.090 .010 (2.286 .254)
(Connect to any ground or power plane for optimum thermal dissipation)
0 to 8
.050 .010 (1.270 .254) .0165 .0035 (.4191 .0889) .033 .017 (.838 .432)
.0025 .0015 (.0635 .0381)
Detail A
16-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 16C
.810 MAX (20.574 MAX)
.295 .010 (7.493 .254) .050 .005 (1.270 .127) .035 .010 (.889 .254) BASE PLANE .125 MIN (3.175 MIN) .018 .002 (.457 .051) SEATING PLANE .100 BSC (2.540 BSC) .300 .010 (7.620 .254)
PIN 1 .200 MAX (5.080 MAX)
.010 .002 (.254 .051)
HOLT INTEGRATED CIRCUITS 9
HI-318X PACKAGE DIMENSIONS
inches (millimeters)
16-PIN CERDIP
Package Type: 16D
.790 MAX. (20.006 MAX.) .050 MAX. (1.27 MAX.)
.005 MIN. (.127 MIN.)
.288 .005 (7.315 .125)
.056 TYP. (1.422 TYP.)
.100 .010 (2.54 .254)
.310 .010 (7.874 .254) .180 MAX. (4.572 MAX.)
.200 MAX. (5.080 MAX.)
.015 MIN. (.381 MIN.)
.125 MIN. (3.175 MIN.)
.018 .003 (.457 .760)
0 to 15
.010 .002 (.254 .051)
28-PIN PLASTIC PLCC
Package Type: 28J
PIN NO. 1 .045 x 45 PIN NO. 1 IDENT .045 x 45 .050 .005 (1.27 .127) .031 .005 (.787 .127)
.490 .005 (12.446 .127) SQ.
.453 .003 (11.506 .076) SQ.
.017 .004 (.432 .102) SEE DETAIL A
.009 .011
.173 .008 (4.394 .203) DETAIL A .410 .020 (10.414 .508)
.015 .002 (.381 .051) .020 MIN (.508 MIN) R .025 .045
HOLT INTEGRATED CIRCUITS 10
HI-318X PACKAGE DIMENSIONS
inches (millimeters)
28-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 28S
.020 INDEX (.508 INDEX)
PIN 1
.080 .020 (2.032 .508)
PIN 1
.050 .005 (1.270 .127) .451 .009 (11.455 .229) SQ. .050 BSC (1.270 BSC) .008R .006 (.203R .152) .040 x 45 3PLS (1.016 x 45 3PLS) .025 .003 (.635 .076)
32-PIN J-LEAD CERQUAD
Package Type: 32U
31 32 1 2
.450 .008 (11.430 .203) .488 .008 (12.395 .203)
.420 .012 (10.668 .305)
.588 .008 (14.935 .203) .550 .009 (13.970 .229) .190 MAX. (4.826) MAX. .083 .009 (2.108 .229)
.040 TYP. (1.016) TYP. .019 .003 .050 TYP. (.483 .076) (1.270) TYP. .520 .012 (13.208 .305)
HOLT INTEGRATED CIRCUITS 11

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